1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a transistor fabrication technique in which nitrogen is incorporated into the silicon gate to provide an advantageous impurity barrier without significantly degrading the transistor performance.
2. Description of the Relevant Art
The conventional fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active regions and isolation regions through an isolation process such as field oxidation or shallow trench isolation. After the isolation and active regions have been formed, the active regions may be further divided into n-well active regions and p-well active regions by implanting n-type dopants and p-type dopants into their respective wells. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Thereafter, a plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region effectively dividing the active region into a pair of source/drain regions disposed on either side of each gate structure and a channel region disposed below each gate structure. After formation of the polysilicon gates, a p-type source/drain implant is performed to introduce p-type impurities into the source/drain regions of the n-wells and an n-type source/drain implant is performed to introduce n-type impurities into the source/drain regions of the p-wells. The dopant species used in conventional transistor processing typically include phosphorus and arsenic for n-type impurities and boron for p-type impurities.
As transistor geometries shrink below 0.5 micron, the limitations of conventional transistor processing become more and more apparent. As the thickness of the gate oxide decreases below 100 angstroms, devices become more susceptible to diffusion of impurities contained within the gate structure across the gate oxide and into the active area of the transistor. This problem is especially acute for gate structures into which boron is implanted (e.g., p+ polysilicon gates) because of the relatively high rate at which boron diffuses through silicon and silicon dioxide. In addition, it is believed that many loosely formed bonds exist at the interface between the gate oxide structure and the polysilicon gate structure in conventionally formed transistors. The presence of these loosely formed bonds is believed to contribute to undesirable transistor characteristics such as susceptibility to voltage breakdown. Still further, as devices become smaller and more densely packed upon a semiconductor substrate surface, it becomes increasingly important to minimize the leakage current of each individual transistor. It is believed that leakage current can be created by a scattering effect that occurs as electrons traverse the channel between a device's source region and drain region. As the number of transistor devices within a single integrated circuit increases, leakage current can become significant enough to raise the temperature of the semiconductor substrate slowing the device and, eventually, raising the temperature above the operational limit of the device.
Therefore, it would be highly desirable to fabricate MOS transistors in a manner that reduced or eliminated diffusion from a gate structure to an underlying active region of the transistor, improved the bond structure of the polysilicon gate oxide interface thereby improving the characteristics of the interface, and increased the source/drain drive current without a corresponding increase in leakage current. It would be further desirable if the fabrication technique selected also facilitated the producing of deep sub-micron transistor channel lengths. In the sub-micron region, the short transistor channels can be rendered effectively non-functional if the source/drain impurities diffuse laterally through the channel. Accordingly, it would be beneficial if the fabrication technique selected limited or prevented lateral substantial diffusion of source/drain impurity distributions thereby reducing concerns over post source/drain high temperature processing. It would be further desirable if the selected fabrication technique did not result in an undue increase in the sheet resistivity of the source/drain regions.